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 PCS3P2042B LCD Panel EMI Reduction IC
Features
* FCC approved method of EMI attenuation. * Provides up to 15dB of EMI suppression. * Generates a low EMI spread spectrum clock of the input frequency. * Input frequency range: 30MHz - 110MHz. * Output frequency range: 30MHz - 110MHz * Optimized for 32.5MHz, 54MHz, 65MHz, 74MHz and 108MHz pixel clock frequencies. * Internal loop filter minimizes external components and board space. * Eight selectable high spread ranges up to 2%. * Selectable spread options: Down Spread and Center Spread * SSON# control pin for spread spectrum enable and disable options. * Low cycle-to-cycle jitter. * 3.3V 0.3V operating range. * CMOS design. * Supports most mobile graphic accelerator and LCD timing controller specifications. * Available in 8-pin TSSOP Package. The PCS3P2042B is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The PCS3P2042B reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The PCS3P2042B allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. The PCS3P2042B uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The PCS3P2042B modulates the output of a single PLL in order to "spread" the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal's bandwidth is called `spread spectrum clock generation.'
Applications
The PCS3P2042B is targeted towards digital flat panel applications for notebook PCs, palm-size PCs, office automation equipments and LCD monitors.
VDD SR0 CP1 CP0 SSON#
Product Description Block Diagram
Modulation CLKIN
PLL
Frequency Divider Feedback Divider
Phase Detector
Loop Filter
VCO
Output Divider ModOUT
VSS
(c)2010 SCILLC. All rights reserved. JANUARY 2010 - Rev. 2
Publication Order Number: PCS3P2042/D
PCS3P2042B
Pin Configuration
CLKIN 1 CP0 2 PCS3P2042B CP1 3 VSS 4
8
VDD
7 SR0 6 5
ModOUT SSON#
Pin Description
Pin# 1 2 3 4 5 6 7 8 Pin Name CLKIN CP0 CP1 VSS SSON# ModOUT SR0 VDD Type I I I P I O I P Description External reference frequency input. Connect to externally generated reference signal. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. Ground to entire chip. Connect to system ground. Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. Spread spectrum clock output. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. Power supply for the entire chip.
Modulation Selection
Spreading Range ( %) CP0 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 SR0 32.5MHz 0 1 0 1 0 1 0 1 1.75 1.89 1.39 2.1 0.74 1.1 0.32 0.58 54MHz 1.53 1.7 1.2 1.85 0.6 0.93 0.3 0.5 65MHz 1.41 1.55 1.1 1.7 0.57 0.86 0.28 0.45 81MHz 1.27 1.4 1.0 1.55 0.52 0.77 0.26 0.4 108MHz 1.1 1.2 0.9 1.35 0.45 0.68 0.23 0.36 (FIN /40) * 62.89 KHz Modulation Rate (KHz)
Rev. 2 | Page 2 of 7 | www.onsemi.com
PCS3P2042B
Spread Spectrum Selection
The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, PCS3P2042B is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat panel operating at 65MHz (FIN) clock speed. A spreading selection of CP0=0, CP1=1 and SR0=0 provides a percentage deviation of 1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35MHz at a modulation rate of 102.19KHz. Refer to Modulation Selection Table. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
+3.3V
65MHz from graphics accelerator
1 CLKIN 2 CP0 3 CP1 4 VSS
VDD SR0
8 7 0.1 F
ModOUT 6 SSON# 5
Modulated 65MHz signal with 1.00% deviation and modulation rate of 102.19KHz. This signal is connected back to the spread spectrum input pin (SSIN) of the graphics accelerator.
PCS3P2042B
Digital control for the SS enable or disable.
Rev. 2 | Page 3 of 7 | www.onsemi.com
PCS3P2042B
Absolute Maximum Ratings Symbol
VDD, VIN TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Rating
-0.5 to +4.6 -65 to +125 260 150 2
Unit
V C C C KV
Voltage on any input pin with respect to Ground
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Operating Conditions Symbol
VDD TA
Parameter
Supply Voltage with respect to Ground Operating temperature Junction temperature Thermal Resistance Commercial
Min
3.0 0
Typ
3.3
Max
3.6 +70
Unit
V C
TJ
Commercial
TSSOP
79.80
C
JC
TSSOP
124
C/W
Rev. 2 | Page 4 of 7 | www.onsemi.com
PCS3P2042B
DC Electrical Characteristics Symbol Parameter
VIL VIH IIL IIH VOL VOH IDD ICC VDD tON ZOUT Input low voltage Input high voltage Input low current (pull-up resistor on inputs CP0, CP1 and SR0) Input high current (pull-down resistor on input SSON#) Output low voltage ( IOL = 8mA) Output high voltage ( IOH = -8mA) Static supply current (CLKIN pulled LOW) Dynamic supply current (3.3V and 10pF loading) Operating voltage Power-up time (first locked cycle after power up) Clock output impedance 35 6 3.0 15 3.3 2.5 300 22 3.6 3
Min
VSS - 0.3 2.0
Typ
Max
0.8 VDD + 0.3 -50 50 0.4
Unit
V V A A V V A mA V mS
AC Electrical Characteristics Symbol
fIN fOUT
1 tLH
Parameter
Input Clock frequency Output Clock frequency Output rise time (measured between 20% to 80%) Output fall time (measured between 80% to 20%) Jitter (cycle-to-cycle) Output duty cycle <50MHz 50MHz
Min
30 30 1.1 0.8
Typ
74 74 1.5 1.2
Max
110 110 2 1.8 250 200
Unit
MHz MHz nS nS pS %
tHL
1
tJC tD
45
50
55
Note: 1. tLH and tHL are measured into a capacitive load of 10pF
Rev. 2 | Page 5 of 7 | www.onsemi.com
PCS3P2042B
Package Information 8-lead TSSOP
H
E D A2 A e B A1 L C
Dimensions Symbol Min A A1 A2 B c D E e H L 0.002 0.033 0.008 0.004 0.114 0.169 Inches Max 0.043 0.006 0.037 0.012 0.008 0.122 0.177 0.05 0.85 0.19 0.09 2.90 4.30 Millimeters Min Max 1.10 0.15 0.95 0.30 0.20 3.10 4.50
0.026 BSC 0.252 BSC 0.020 0 0.028 8
0.65 BSC 6.40 BSC 0.50 0 0.70 8
Rev. 2 | Page 6 of 7 | www.onsemi.com
PCS3P2042B
Ordering Information Part Number
PCS3P2042BG-08TT PCS3P2042BG-08TR
Top Marking
CEL CEL
Package Type
8-Pin TSSOP, TUBE, Green 8-Pin TSSOP, TAPE & REEL, Green
Temperature
0 to +70 C C 0 to +70 C C
A "microdot" placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free.
Note: Many ON Semiconductor products are protected by issued patents or applications for patent. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. U.S Patent Pending; Timing-Safe and Active Bead are trademarks of PulseCore Semiconductor, a wholly owned subsidiary of ON Semiconductor. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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